1. Field of the Invention
The present invention relates to carrier substrates for use in chip-scale packages and to chip-scale packages including such carrier substrates. Particularly, the present invention relates to silicon carrier substrates. Methods of fabricating chip-scale packages are also within the scope of the present invention.
2. State of the Art
In conventional semiconductor device fabrication processes, a number of distinct semiconductor devices, such as memory chips or microprocessors, are fabricated on a semiconductor substrate, such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the substrate is typically singulated to separate the individual semiconductor devices from one another.
Various post-fabrication processes, such as testing the circuits of each of the semiconductor devices and burn-in processes, may be employed either prior to or following singulation of the semiconductor substrate. These post-fabrication processes may be employed to impart the semiconductor devices with their intended functionality and to determine whether or not each of the individual semiconductor devices meet quality control specifications.
The individual semiconductor devices may then be packaged. Along with the trend in the semiconductor industry to decrease semiconductor device size and increase the density of structures of semiconductor devices, package sizes are also ever-decreasing. One type of semiconductor device package, the so-called “chip-scale package” or “chip-sized package” (“CSP”), consumes about the same amount of real estate upon a substrate as the bare semiconductor device itself. Such chip-scale packages typically include a carrier substrate having roughly the same surface area as the semiconductor device itself. As the carrier substrate of such chip-scale packages is small, electrical connections between the semiconductor device and the carrier substrate are often made by flip-chip type bonds or tape-automated bonding (“TAB”). Due to the typical use of a carrier substrate that has a different coefficient of thermal expansion than the semiconductor substrate of the semiconductor device, these types of bonds may fail during operation of the semiconductor device.
In view of the potential for failure of the flip-chip or TAB electrical connections in chip-scale packages, chip-scale packages that include more flexible electrical connections, such as wire bonds, were developed. An exemplary chip-scale package that includes such flexible electrical connections is disclosed in U.S. Pat. No. 5,685,885 (hereinafter “the '885 Patent”), issued to Khandros et al. on Nov. 11, 1997. The chip-scale package of the '885 Patent may be assembled by orienting and disposing a sheet of interposer material over a wafer including a plurality of semiconductor devices thereon. The bond pads of the semiconductor devices may then be wire-bonded or otherwise flexibly bonded to corresponding contacts of the interposer. The wafer and interposer sheet may then be simultaneously singulated to separate individual semiconductor device packages from each other. The method and devices of the '885 Patent are, however, somewhat undesirable. The package of the '885 Patent includes a semiconductor device, a flexible, sheet-like dielectric interposer, and a substrate. Thus, the likelihood of failure of the semiconductor device is undesirably high. Moreover, the interposer of the package of the '885 Patent may include circuitry thereon to reroute electrical signals to and from the bond pads of the semiconductor device. These circuits may undesirably alter the electrical characteristics of signals transmitted through the bond pads.
Following packaging, the packaged semiconductor devices may be retested or otherwise processed to ensure that no damage occurred during packaging. The testing of individual packaged semiconductor devices is, however, somewhat undesirable since each package must be individually aligned with such testing or probing equipment.
Accordingly, there is a need for a semiconductor packaging process that facilitates testing, probing, and burn-in of semiconductor devices without requiring the alignment of individual semiconductor devices and by which a plurality of reliable chip-scale packages may be substantially simultaneously assembled. An efficient chip-scale packaging process with a reduced incidence of semiconductor device failure is also needed. There is a further need for chip-scale packaged semiconductor devices that consume about the same amount of real estate as the semiconductor devices thereof and that withstand repeated exposure to the operating conditions of the semiconductor device.